Shifted competely connected network (SCCN) : architecture of hierarchical interconnection network to improve the performance of massively parallel computer systems

Abstract

At the current time, finding an alternative computing device with extreme computation power became the main concern of the research community. Therefore, building a computer device able to execute extremely difficult calculations in a short time is required. Presently, massively parallel computer (MPC) systems considered the highest computing devices, and the existence of these systems is important to execute many operations in many sectors such as engineering and science. These systems built based on an internal network called interconnection network which has a particular design represented by the network topology. The performance of these networks affected widely by the network topology. Besides, the cost of these networks influenced by the price of the processing elements (PEs) and the communication links. Thus, the design of the interconnection network topology has a crucial impact on the network cost and performance. Many topologies of interconnection networks have been presented to be used as basic modules in building MPC systems. However, the earlier topologies showed a lack of performance in case of increasing the size of the interconnection network. As a result, hierarchical interconnection networks (HINs) proposed to replace these networks. Currently, many HINs introduced to enhance the performance of MPC systems, however, we still lack a good one. In this research, a hierarchical interconnection network proposed as a basic module (BM) to build a complete parallel computer system. This topology is a completely connected network composed of six nodes and called shifted completely connected network (SCCN), also, it connected hierarchically to produce higher-levels leading to a complete system network. A two-dimensional system with multiple levels is built based on SCCN. The two-dimensional levels which composing this system are network-on-chip level, board-level, cabinet-level, and system-level. The static network performance parameters of these levels evaluated by computer simulators and the obtained results compared to multiple conventional and hierarchical interconnection networks. Moreover, in this research, we presented a three-dimensional design of SCCN based on the proposed topology. Therefore, a three-dimensional network-on-chip (3D-NoC) presented to build higher levels of 3D-SCCN. The static network performance parameters of 3D-NoC level and the higher levels assessed by computer simulators. Furthermore, the obtained results compared to other conventional and hierarchical interconnection networks. The purpose of the comparison is to prove the strength of the proposed topology which showed promising results in many aspects.