Analysis of DC-DC modular structure converters for voltage transients mitigation

Abstract

One module of back converter is simulated using a forward quad-transistor topology. The 1: N stepping-down transformer is an effective component with galvanizing performance. Transistors are fitted with a diode while keeping the coil protected from spikes and fly-back issues. These configurations can be used in a modular structure, thereby reducing power losses of electronic components of the circuit, thus ensuring better analysis while enhancing efficiency and performance, thereby reducing design cost as well as being an integral part of hot swap features. Modules are stacked in parallel at the output for applications that increase the power rating. The proposed model structure of the Input Series Output Parallel (ISOP) module is selected for analysis under both steady and dynamic performance. The areas concentrated and explored in this research of the proposed configuration topology with considering voltage transient spikes and power loses. The circuit is simulated using PSIM Powersimtech with clearly state and emphasizing the modularity and transistors switching. The experiment has been conducted using Arduino Mega board to generate PWM and reduce the cost of the module. The result obtained from the two module using four transistor forward configuration shows the output voltage levels for different duty cycle values. Three value of duty cycle are determined by setting the duty cycle to be at 40% as the benchmark. Then, the duty cycle is set to 30%, 50% and 75%, which is later compared to the benchmark duty cycle, giving the output as expected accordingly. Depending on the switching frequency, the duty cycle and the input voltage, the output voltage will be valid as long as the duty cycle is set exactly at 50%. The current spikes and the output voltage stability are investigated by first determining the full bridge DC-DC converter topology. It shows that by increasing the switching frequency to 10 kHz and keeping the duty cycle to be at 50%, will produce less overshoot and system efficiency of 95% based on the simulation and measurement of the time taken for the output voltage to be at 30% overshot voltage. The input voltage is set to be at 48 V resulting best stability of the two modules connecting in series at the input. The effect of the switching frequency on the output will be optimized as long as the value of the duty cycle is set at 50% which then will reduce the spikes and hence achieving the objectives of this research, but however at the same time increasing the frequency at high level will reduce the output voltage and hence it need control strategy to get maximum power efficiency.